
`include "defines.v"

module mux_width (
    input  wire              rst,
    input  wire [63 :     0] mux_width_i,
    input  wire [2  :     0] width_sel,

    output reg  [`BUS_WIDTH] mux_width_o
);


    always @(*) begin
        if (rst) begin
            mux_width_o = `ZERO_WORD;
        end
        else begin
            case (width_sel)
                3'b000: begin    // b
                    mux_width_o = {{56{mux_width_i[7]}},  mux_width_i[7 : 0]};
                end
                3'b100: begin    //bu
                    mux_width_o = {56'b0,                 mux_width_i[7 : 0]};
                end
                3'b001: begin    // h
                    mux_width_o = {{48{mux_width_i[15]}}, mux_width_i[15 : 0]};
                end
                3'b101: begin    // hu
                    mux_width_o = {48'b0,                 mux_width_i[15 : 0]};
                end
                3'b010: begin    //w
                    mux_width_o = {{32{mux_width_i[31]}}, mux_width_i[31 : 0]};
                end
                3'b110: begin    // wu
                    mux_width_o = {32'b0,                 mux_width_i[31 : 0]};
                end
                3'b011: begin    // d
                    mux_width_o = mux_width_i;
                end
                default: begin
                    mux_width_o = mux_width_i;
                end
            endcase
        end
    end

    
endmodule
